Minimal Instruction Set Computer (MISC)

Minimal instruction set computer (MISC) is a processor architecture with a very small number of basic operations and corresponding opcodes in its instruction set. Such instruction sets are commonly stack-based rather than register-based to reduce the size of operand specifiers.

Key points

Key points of MISC are:

• a minimal instruction set computer is viewed as having 32 or fewer instructions where NOP, RESET and CPUID type instructions
• A MISC CPU cannot have zero instructions as that is a zero instruction set computer
• A MISC CPU cannot have one instruction as that is a one instruction set computer
• The only addressing mode considered acceptable for a MISC CPU to have is load/store, the same as for RISC CPUs
• MISC CPUs can typically have between 64 KB to 4 GB of accessible addressable memory
• Features like Instruction pipelines, branch prediction, out-of-order execution, register renaming and speculative execution do not form a part of MISC CPU

Disadvantages

Disadvantages of MISC design are:

• Instructions tend to have more sequential dependencies, reducing overall instruction-level parallelism

• Optimal features like Instruction pipelines, branch prediction, out-of-order execution, register renaming and speculative execution do not form a part hence, has lower performance

Commercial Usage

MISC design is commercially used as:

• Each STEREO spacecraft includes two P24 MISC CPUs and two CPU24 MISC CPUs

• Most commercially successful MISC was the original INMOS transputer architecture that had no floating-point unit