Verilog vs VHDL (VHSIC Hardware Description Language)

Verilog and VHDL (VHSIC Hardware Description Language) are both hardware description language for hardware modeling.

In general, there are two conclusions:

• Verilog is used extensively for production level projects and in Industry
• VHDL is great for beginners who are yet to develop Hardware Design Principles

Origin

Verilog has its origins in gate and transistor level simulation for digital electronics (logic circuits), and had various behavioral extensions added for verification.

VHDL was the winner in a DoD competition to develop an Hardware Description Language for the VHSIC program and is based on ADA programming language.

Design concept

VHDL uses top-down approach to partition design into small blocks such as:

• Entity: Describe interface signals & basic building blocks
• Architecture: Describe behavior, each entity can have multiple Architectures
• Configuration: Specify different architectures for a single entity.
• Package: Contain user-defined subprograms, constant definitions, and/or type definitions to be used throughout one or more design units

Verilog only has one building block: module

• Modules connect through their port similarly as in VHDL.
• There is only one module per file usually.
• A top level invokes instances of other modules.
• Modules can be specified behaviorally or structurally.
• Behavioral: Define behavior of digital system.
• Structural: Define hierarchical interconnection of modules.

Modeling capacity

VHDL is a high level language (like Python for hardware design)

Verilog is a low level language (like C for hardware design)