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Ravi Arimilli is a Prolific Inventor of Indian origin and Fellow and Chief Architect at IBM. He moved to USA with his family in 1969 and was originally from Andhra Pradesh, India. He holds the record of the 4th highest number of patents issued to a person of Indian origin.
- 4th highest number of patents issued to a person of Indian origin (see complete list)
He is a notable employee of IBM and is one of the 10 active IBM fellows.
Background of Ravi Arimilli
Ravi Arimilli was born in Andhra Pradesh, India and moved to USA in 1969 at an early age of 6 years. He completed his Bachelor's degree from ouisiana State University in USA and had worked at IBM.
Ravi's brother Baba Arimilli works at IBM and is a Profilic Inventor as well. Baba Arimilli has over 40 patents issued to his name. The Arimilli Brothers have made a major contribution to IBM's patents.
First patent: 1992
Education: Louisiana State University
Award: IBM Award
Ravi Arimilli is well known in the Industry for his work on:
- Power4chip which was considered a complicated processor in early 2000s.
- POWER5 microprocessor
- His work on Power architectures helped IBM become a leader in Linux systems.
Full name of Ravi is "Ravi Kumar Arimilli".
Patents by Ravi Arimilli
Ravi Arimilli got his first patent in 1992 but his drive to publish an incredible number of patents started from 1998. In 1998, he published 18 patents and was awarded:
- Inventor of the year at IBM in 1998
Since 1998, he continued publishing patents with an average of 23 patents a year since 1998.
Research areas of Ravi Arimilli are:
- Symmetric multiprocessing (SMP)
- System structures
- Cache and memory hierarchies
- System bus protocols
Some example patents by Ravi Arimilli are:
- Techniques for cache injection in a processor system from a remote node
- Techniques for cache injection in a processor system using a cache injection instruction
- Techniques for cache injection in a processor system
- Management of process-to-process inter-cluster communication requests
- Remote update programming idiom accelerator with allocated processor resources
- Use of a helper thread to asynchronously compute incoming data
- Compiler providing idiom to idiom accelerator
- Wake-and-go mechanism with hardware private array
- Wake-and-go mechanism with dynamic allocation in hardware private array
- Performing a partial cache line storage-modifying operation based upon a hint
- Supporting multiple high bandwidth I/O controllers on a single chip
- Computation table for block computation
- Block driven computation with an address generation accelerator
- Dynamic runtime modification of array layout for offset
- Programming Language Exposing Idiom Calls
- Techniques for indirect data prefetching
With this article at OpenGenus, you must have a strong idea of background of Ravi Arimilli.