instruction set - OpenGenus IQ: Computing Expertise & Legacy

Why learn assembly instructions?

In this article at OpenGenus, we have explained how learning assembly instructions can be useful and who should learn it in this age of high level programming languages.

instruction set

Matrix Multiplication in Assembly

In this article at OpenGenus, we have explained how to implement Matrix Multiplication in Assembly. We have provided the complete assembly code to multiply 2 3x3 matrices as well.

instruction set

Array in x86 Assembly

In this article at OpenGenus, we have explained how to implement an Array in x86 Assembly Programming Language. This gives a strong insight on how array function behind the high level programming languages.

instruction set

XCHG - Exchange Memory

In this article at OpenGenus, we have explained the concept of XCHG instruction in x86 processor that is used to swap contents between two registers or memory locations.

Computer Architecture

Number of Clock Cycles in Assembly Instructions

In this article at OpenGenus, we have listed the Number of Clock Cycles in different Assembly Instructions like LEA, XCHG and others.

instruction set

Number of Clock Cycles in Arithmetic Operations

In this article at OpenGenus, we have listed the Number of Clock Cycles in Arithmetic Operations. This is an important information to understand which operation to use and which one to avoid based on performance.

instruction set

x86 LEA - Load Effective Address

In this article at OpenGenus, we have explained the concept of LEA assembly instruction which is used in x86 processors.

instruction set

Exit program in Assembly code

In this article at OpenGenus, we have explored how to exit a program written in Assembly.

C++

MOVZX - Move with Zero Extend

In this article at OpenGenus, we have explored the concept of MOVZX assembly instruction in depth with code examples.

instruction set

Explicitly parallel instruction computing (EPIC)

EPIC (Explicitly Parallel Instruction Computing) is a 64-bit microprocessor instruction set which is an improvement to the VLIW (Very Large Instruction Word) architecture. It has been developed by Intel and Hewlett Packard. It uses speculative loading, predication, and explicit parallelism

instruction set

Very long instruction word (VLIW)

Very long instruction word (VLIW) is an instruction set architecture designed to take full advantage of instruction level parallelism in form of pipelining, multiple processors, superscalar implementation and multiple independent operations. It has its advantages and disadvantages and is used widely

instruction set

Minimal Instruction Set Computer (MISC)

Minimal instruction set computer (MISC) is a processor architecture with a very small number of basic operations and corresponding opcodes in its instruction set. MISC has its own advantages and disadvantages. It is commercially used as STEREO and INMOS transputer

instruction set

One Instruction Set Computer (OISC)

One Instruction Set Computer (OISC) is a computer architecture that has only one instruction in its instruction set. It is based on bit manipulating machine, transport triggered architecture and arithmetic based turing complete machines. It has its own advantages and used commercially as high subleq

instruction set

Zero instruction set computer (ZISC)

Zero instruction set computer (ZISC) is a computer architecture based on two fundamental ideas like pattern matching and absence of micro instructions. ZISC has its own advantages and is commercially used by IBM in ZISC35 and by Intel s NI1000. CM1K another ZISC has been developed recently.

instruction set

Examples of Instruction Sets

We have demonstrated examples of instruction set architectures from various categories such as RISC, CISC, MISC, VLIW, EPIC, OISC and ZISC. Examples include ARM, MIPS, OpenRISC, SPARC, x86, z architecture, Intel 8080, Transputer, Transmeta Crusoe, Elbrus 2000, Itanium, Cryptoleq, NI1000 and CM1K.

instruction set

7 Types of Instruction Set

Instruction sets are Reduced Instruction Set Computer (RISC), Complex Instruction Set Computer (CISC), Minimal instruction set computers (MISC), Very long instruction word (VLIW), Explicitly parallel instruction computing (EPIC), One instruction set computer (OISC) and Zero instruction set computer

Computer Architecture

Complex Instruction Set Computer (CISC) architecture explained

CISC Complex Instruction Set Computer architecture focuses on reducing the number of instructions per program It has emphasis on hardware design, has multi clock complex instructions, memory to memory instructions, high cycles per second, small code size and uses transistors for storing instructions

Computer Architecture

Reduced Instruction Set Computer (RISC) architecture explained

RISC (Reduced Instruction Set Computer) architecture focuses on reducing the number of cycles per instruction. It has emphasis on software design, has single clock, reduced instructions only, register to register independent instruction, low cycles per second and large code size. See a RISC example