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Explicitly parallel instruction computing (EPIC)

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EPIC (Explicitly Parallel Instruction Computing) is a 64-bit microprocessor instruction set which is an improvement to the VLIW (Very Large Instruction Word) architecture. It provides up to 128 general and floating point unit registers and uses speculative loading, predication, and explicit parallelism to accomplish its computing tasks.

It has been, originally, developed by Intel and Hewlett Packard.

By comparison, current 32-bit CISC and RISC microprocessor architectures depend on 32-bit registers, branch prediction, memory latency, and implicit parallelism, which are considered a less efficient approach in microarchitecture design.


By 1989, researchers at HP recognized that reduced instruction set computer (RISC) architectures were reaching a limit at one instruction per cycle. They began an investigation into a new architecture named EPIC. The basis for the research was VLIW, in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was:

  • to move the complexity of instruction scheduling from the CPU hardware to the software compiler
  • exploit instruction level parallelism (ILP) by using the compiler to find and exploit additional opportunities for parallel execution

The idea is that a compiler can do the instruction scheduling statically (with help of trace feedback information). This results in:

  • no need of complex scheduling circuitry in the CPU
  • frees up space and power for other functions, including additional execution resources.

Improvements over Very Large Instruction Word (VLIW)

EPIC architectures add several features to get around the deficiencies of VLIW:

  • Each group of multiple software instructions is called a bundle. Each of the bundles has a stop bit indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.

  • A software prefetch instruction is used as a type of data prefetch. This prefetch increases the chances for a cache hit for loads, and can indicate the degree of temporal locality needed in various levels of the cache.

  • A speculative load instruction is used to speculatively load data before it is known whether it will be used (bypassing control dependencies), or whether it will be modified before it is used (bypassing data dependencies).

  • A check load instruction aids speculative loads by checking whether a speculative load was dependent on a later store, and thus must be reloaded.

The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP:

  • Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.

  • Delayed exceptions, using a not a thing bit within the general purpose registers, allow speculative execution past possible exceptions.

  • Very large architectural register files avoid the need for register renaming.

  • Multi-way branch instructions improve branch prediction by combining many alternative branches into one bundle.

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OpenGenus Tech Review Team

The official account of OpenGenus's Technical Review Team. This team review all technical articles and incorporates peer feedback. The team consist of experts in the leading domains of Computing.

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