OpenGenus IQ: Learn Algorithms, DL, System Design (Page 152)

Chebyshev distance

Chebyshev distance is a distance metric which is the maximum absolute distance in one dimension of two N dimensional points. It has real world applications in Chess, Warehouse logistics and many other fields. It is known as Tchebychev distance, maximum metric, chessboard distance and L∞ metric.

similarity measurement

Euclidean distance (L2 norm)

Euclidean distance is the shortest distance between two points in an N dimensional space also known as Euclidean space. It is used as a common metric to measure the similarity between two data points and used in various fields such as geometry, data mining, deep learning and others.

similarity measurement

Manhattan distance [Explained]

Manhattan distance (L1 norm) is a distance metric between two points in a N dimensional vector space. It is the sum of the lengths of the projections of the line segment between the points onto the coordinate axes. It was introduced by Hermann Minkowski. It is used in regression analysis

tpu

What is Neural processing unit (NPU)?

A neural processing unit (NPU) is a microprocessor that specializes in the acceleration of machine learning algorithms. Examples include TPU by Google, NVDLA by Nvidia, EyeQ by Intel, Inferentia by Amazon, Ali-NPU by Alibaba, Kunlun by Baidu, Sophon by Bitmain, MLU by Cambricon, IPU by Graphcore

Software Engineering

Laws similar to Moore's Law

Laws similar to Moore's Law are Eroom's law, Engelbart's law, Haitz's law, Koomey's law, Carlson curve, Swanson's law, Pollack's rule, Wirth's law / Page's law / Gates's law / May's law / The great Moore's law compensator (TGMLC), Keck's law, Nielsen's Law and Dennard scaling.

Software Engineering

Moore's second law or Rock's law

Moore's second law or Rock's law, states that the cost of a semiconductor chip fabrication plant doubles every four years. Research and Development, manufacturing and testing have increased steadily with each new generation of chips Rising manufacturing costs are an important consideration

computational model

Stack Machine: A computational model

A Stack Machine is a computational model that uses a last-in, first-out stack to hold short-lived temporary values. Most of its instructions assume that operands will be from the stack, and results placed in the stack. It has its own advantages such as it does not need any addressing

Software Engineering

RISC vs CISC architecture

RISC and CISC differ based on the following factors: approach to improve computing performance, hardware and Software focus and hardware specifications. In general, both are equally useful. CISC is commonly used in automation devices whereas RISC is used in video and image processing applications.

Software Engineering

Moore's law

Moore's law is the observation that the number of transistors in a dense integrated circuit doubles about every two years. It states that computing would dramatically increase in power, and decrease in relative cost, at an exponential rate. It is named after Gordon Earle Moore, founder of Intel

Algorithms

Manacher's Algorithm

Manacher's Algorithm is an efficient algorithm to find the longest palindromic substring in a given string in linear time and linear space complexity. It uses key ideas from dynamic programming to solve the problem efficiently.

Algorithms

Boyer Moore String Search Algorithm

Boyer Moore string search algorithm is an efficient string searching algorithm which was developed by Robert S. Boyer and J Strother Moore in 1977. The time complexity is linear in terms of length of data to be searched and preprocessing complexity is linear as well

gpu

Central Processing Unit (CPU) vs Graphics Processing Unit (GPU) vs Tensor Processing Unit (TPU)

Central Processing Unit (CPU), Graphics Processing Unit (GPU) and Tensor Processing Unit (TPU) are processors with a specialized purpose and architecture. We have compared these in respect to Memory Subsystem Architecture, Compute Primitive, Performance, Purpose, Usage and Manufacturers.

Software Engineering

CAP theorem (Brewer's theorem)

The CAP theorem (or Brewer Theorem) is the idea that a distributed computing system is not able to provide partition tolerance, consistency and availability at the same time. It was developed in 2000 by Eric Allen Brewer. CAP theorem has applications in database and server infrastructure

instruction set

Explicitly parallel instruction computing (EPIC)

EPIC (Explicitly Parallel Instruction Computing) is a 64-bit microprocessor instruction set which is an improvement to the VLIW (Very Large Instruction Word) architecture. It has been developed by Intel and Hewlett Packard. It uses speculative loading, predication, and explicit parallelism

instruction set

Very long instruction word (VLIW)

Very long instruction word (VLIW) is an instruction set architecture designed to take full advantage of instruction level parallelism in form of pipelining, multiple processors, superscalar implementation and multiple independent operations. It has its advantages and disadvantages and is used widely

TensorFlow

How TensorFlow uses Graph data structure concepts?

In this article, we explain various concepts in TensorFlow such as tensors, dataflow graphs and several optimizations such as decision tree pruning and demonstrate the use of graph data structure and algorithm concepts in TensorFlow

instruction set

Minimal Instruction Set Computer (MISC)

Minimal instruction set computer (MISC) is a processor architecture with a very small number of basic operations and corresponding opcodes in its instruction set. MISC has its own advantages and disadvantages. It is commercially used as STEREO and INMOS transputer

instruction set

One Instruction Set Computer (OISC)

One Instruction Set Computer (OISC) is a computer architecture that has only one instruction in its instruction set. It is based on bit manipulating machine, transport triggered architecture and arithmetic based turing complete machines. It has its own advantages and used commercially as high subleq

instruction set

Zero instruction set computer (ZISC)

Zero instruction set computer (ZISC) is a computer architecture based on two fundamental ideas like pattern matching and absence of micro instructions. ZISC has its own advantages and is commercially used by IBM in ZISC35 and by Intel s NI1000. CM1K another ZISC has been developed recently.

instruction set

Examples of Instruction Sets

We have demonstrated examples of instruction set architectures from various categories such as RISC, CISC, MISC, VLIW, EPIC, OISC and ZISC. Examples include ARM, MIPS, OpenRISC, SPARC, x86, z architecture, Intel 8080, Transputer, Transmeta Crusoe, Elbrus 2000, Itanium, Cryptoleq, NI1000 and CM1K.

instruction set

7 Types of Instruction Set

Instruction sets are Reduced Instruction Set Computer (RISC), Complex Instruction Set Computer (CISC), Minimal instruction set computers (MISC), Very long instruction word (VLIW), Explicitly parallel instruction computing (EPIC), One instruction set computer (OISC) and Zero instruction set computer

Computer Architecture

Complex Instruction Set Computer (CISC) architecture explained

CISC Complex Instruction Set Computer architecture focuses on reducing the number of instructions per program It has emphasis on hardware design, has multi clock complex instructions, memory to memory instructions, high cycles per second, small code size and uses transistors for storing instructions

Computer Architecture

Reduced Instruction Set Computer (RISC) architecture explained

RISC (Reduced Instruction Set Computer) architecture focuses on reducing the number of cycles per instruction. It has emphasis on software design, has single clock, reduced instructions only, register to register independent instruction, low cycles per second and large code size. See a RISC example

Machine Learning (ML)

Key ideas that makes Graphics Processing Unit (GPU) work so fast

We have explored the key ideas that are used in Graphics Processing Unit to make it so fast. Ideas include many cores in parallel, pack cores full of ALUs by sharing instruction stream by explicit SIMD vector instruction and avoid latency stalls by interleaving execution of many groups.

Machine Learning (ML)

Basic Graphics Processing Unit (GPU) design concepts

we have explored some of the basic architecture concepts in Graphics Processing Unit (GPU) such as graphics pipeline, vector processing, primitive processing, rasterization, fragment processing, pixel operations, graphics architecture and shader programming model There are five basic graphics entity